The present invention relates generally to manufacture of integrated circuit packages, and more particularly, to a method and system for temperature cycling at an interface between an IC (integrated circuit) die and an underfill material of an IC (integrated circuit) package that accurately reflects temperature cycling during operation of the integrated circuit on the IC die.
Referring to FIG. 1, an IC (integrated circuit) package 100 is comprised of an IC (integrated circuit) die 102 mounted to an IC (integrated circuit) package housing 104 with an underfill material 106. The IC package 100 provides connection between pins 108 of the IC package 100 to nodes of the integrated circuit fabricated on the IC die 102, as known to one of ordinary skill in the art of electronics. During operation of the integrated circuit on the IC die 102, power is dissipated, and the IC die 102 heats up.
Temperature cycling is performed for assessing the effect of thermal stress on the IC package 100 as the temperature of the IC die 102 varies from a low-end temperature such as xe2x88x9265xc2x0 Celsius to a high-end temperature such as 150xc2x0 Celsius. Referring to FIG. 2, in the prior art, to assess the effect of the high-end temperature on the IC package 100, the IC package 100 is placed within a heating chamber 110. A heat source 112 within the heating chamber 110 changes the environmental temperature within the heating chamber 110. Then, the temperature of the whole IC package 100 including the whole IC die 102 within the IC package 100 gradually heats up from being placed within the heating chamber 110. Typically, the whole IC package 100 heats up to the enviromental temperature within the heating chamber 110 after the IC package 100 has been within the heating chamber for several minutes.
Referring to FIG. 3, an enlarged cross sectional view of the IC die 102 includes active device regions 122 fabricated from a front side 124 of the IC die 102. The IC die 102 is comprised of a semiconductor material, such as silicon for example, for fabricating integrated circuit structures therein. The active device regions 122 are typically shallow from the front side 124 of the semiconductor die. For example, the active device regions 122 may be comprised of drain and source junctions of MOSFETs (metal oxide semiconductor field effect transistors) having depths in a range of hundreds of nanometers to micrometers, as known to one of ordinary skill in the art of integrated circuit fabrication.
A back side 126 of the semiconductor die 102 is opposite to the front side 124 of the semiconductor die 102. In addition, an interlevel dielectric material 128, comprised of silicon dioxide (SiO2) for example, is formed on the front side of the semiconductor wafer. The interlevel dielectric material 128 is comprised of the dielectric material through which interconnect structures are formed, and the interlevel dielectric material 128 is also comprised of encapsulating dielectric material, as known to one of ordinary skill in the art of integrated circuit fabrication.
Typically, within an IC package, the front side 124 of the IC die 102 is mounted to the IC package via an underfill material 130, as known to one of ordinary skill in the art of IC package manufacture. The underfill material 130 is comprised of a material for bonding the IC die 102 to the housing of the IC package. The interlevel dielectric material 128 is disposed at the interface between the front side 124 of the IC die 102 and the underfill material 130 of the IC package.
FIG. 4 shows an example IC package named as a xe2x80x9cflip-chipxe2x80x9d 150, as known to one of ordinary skill in the art of IC package manufacture. In the flip-chip IC package 150, the IC die 102 is mounted to the IC package housing 106 with the underfill material 130. Each of a plurality of pins 152 of the flip chip IC package 150 provides connection to a respective node of the integrated circuit on the IC die 102 via a respective one of a grid array of contact balls 125. In the flip-chip IC package 150, the front-side 124 of the IC die 102 is mounted to the underfill material 130 while the back side 126 of the IC die 102 is exposed. Referring to FIGS. 3 and 4, an interlevel dielectric material is formed on the front side of the IC die 102 mounted on the flip-chip IC package 150 (similar to the interlevel dielectric material 128 of FIG. 3), and such an interlevel dielectric material 128 is at the interface between the front-side 124 of the IC die 102 and the underfill material 130 of the flip-chip IC package 150.
Further referring to FIGS. 3 and 4, during operation of the integrated circuit on the IC die 102, the front-side 124 of the IC die heats up rapidly as power is dissipated within the active device regions 122 during operation of the integrated circuit on the IC die 102. In addition, the power dissipated through such active device regions 122 is dramatically increasing as the clocking speed of integrated circuits, such as for microprocessors for example, is increasing with technological advancement. Thus, for many modem integrated circuits fabricated on the IC die 102, the front-side 124 of the IC die 102 heats up rapidly, such as in seconds or in less than a second, during operation of the integrated circuit on the IC die 102.
In addition, such rapid heating of the front-side 124 from operation of the integrated circuit on the IC die 102 is localized to the interface between the front side 124 of the IC die 102 and the underfill material 130. The underfill material 130 is typically comprised of a material such as epoxy which is not a good heat conductor. The interlevel dielectric material 128 absorbs the heat generated at the active device regions 122 of the front-side 124 of the IC die 102. Thus, the interface between the front side 124 of the IC die 102 and the underfill material 130 including the interlevel dielectric material 128 heats up rapidly from operation of the integrated circuit on the IC die 102.
Such rapid heating at the interface between the front side 124 of the IC die 102 and the underfill material 130 including the interlevel dielectric material 128 causes thermal stress at such an interface. For example, with such thermal stress, the underfill material 130 may undesirably delaminate from the IC die 102 such that the IC die 102 is not securely mounted to the IC package. It is desired to assess the effect of such thermal stress from the rapid heating localized at the interface between the front side 124 of the IC die 102 and the underfill material 130 including the interlevel dielectric material 128 from operation of the integrated circuit on the IC die 102.
However, the prior art mechanism of temperature cycling to the high-end temperature within the heating chamber 110 of FIG. 2 does not accurately simulate such rapid heating localized at the interface between the front side 124 of the IC die 102 and the underfill material 130 including the interlevel dielectric material 128 from operation of the integrated circuit on the IC die 102. With the heating chamber 110 of FIG. 2 in the prior art, the whole IC package 100 is heated inward from the temperature gradient of the heated environmental temperature within the heating chamber 110. Thus, the heating is not localized to the interface between the front side 124 of the IC die 102 and the underfill material 130 including the interlevel dielectric material 128. In addition, such heating of the IC package 100 within the heating chamber 110 of FIG. 2 in the prior art is gradual over a time period of minutes. Thus, heating is not rapid over a time period of seconds or less than a second.
Thus, a temperature cycling mechanism is desired for more accurately simulating the rapid heating localized at the interface between the front side 124 of the IC die 102 and the underfill material 130 including the interlevel dielectric material 128 from operation of the integrated circuit on the IC die 102.
Accordingly, in a general aspect of the present invention, a temperature cycling mechanism uses laser energy for more accurately simulating the rapid heating localized at the interface between the front side of the IC die and the underfill material of the IC package including the interlevel dielectric material at the front side of the IC die, from operation of the integrated circuit on the IC die.
In one embodiment of the present invention, in a method and system for temperature cycling at an interface between a front side of an IC (integrated circuit) die and an underfill material of an IC (integrated circuit) package, a front face of the IC die has an interlevel material thereon, and the interlevel material is at the interface between the IC die and the underfill material. A laser source generates a laser beam, and the laser beam is directed from the laser source to the interlevel material such that the interlevel material absorbs the laser beam to become heated from the absorption of the laser beam. A thermometer measures a temperature of the interlevel material. A laser controller is used for adjusting at least one of a pulse duration and a pulse repetition rate of the laser beam until the temperature of the interlevel material reaches a predetermined high-end temperature.
The present invention may be used to particular advantage when the IC package is a flip-chip such that the laser beam is directed toward a back-side of the IC die mounted on the IC package with the back-side of the IC die being exposed. In that case, the laser beam is comprised of a light having a wavelength that is within a transmission region of a semiconductor material of the IC die such that the laser beam is substantially transmitted through the semiconductor material of the IC die to reach the interlevel material on the front side of the IC die.
In an example embodiment, the semiconductor material of the IC die is comprised of silicon having the transmission region for wavelength of light being in a range of from about 1 xcexcm (micrometer) to about 20 xcexcm (micrometer). In that case, the laser beam is from a CO2 laser source for generating light having a wavelength of about 10.6 xcexcm (micrometer). The laser beam applied on the back-side of the IC die has a power of about 15 Watts, a pulse duration of about 100 xcexcs (microsecond), and a pulse repetition rate of about 1 Kilo-Hertz, for generating the predetermined high-end temperature of about 150xc2x0 Celsius at the interlevel material comprised of silicon dioxide.
In another embodiment of the present invention, the laser beam is applied toward the back-side of the IC die for a predetermined time period, and a microscopy image of the interface between the front side of the IC die and the underfill material of the IC package is generated for detecting delamination of the underfill material from the IC die resulting from the temperature cycling.
In this manner, laser energy is applied and absorbed at a localized area (i.e., the interlevel dielectric material at the interface between the front side of the IC die and the underfill material of the IC package). In addition, with application of the laser beam to the localized area, the temperature of such a localized area heats up rapidly over a time period of seconds or less than a second. Thus, the temperature cycling mechanism of the present invention more accurately simulates the rapid heating localized at the interface between the front side of the IC die and the underfill material of the IC package including the interlevel dielectric material at the front side of the IC die from operation of the integrated circuit on the IC die.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.